49FCT3805DPYGI, Clock Divider CMOS, 2-Input, 20-Pin SSOP [49FCT3805DPYGI]; 254-4924

The Renesas Electronics 3.3 volt clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a heartbeat monitor fordiagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. It offers low capacitance inputs. It is designed for high speed clock distribution where signal quality and skew are critical. It also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple recievers with low skew and high signal quality.

Advanced CMOS technology

Guaranteed low skew < 200 ps (max)

Very low propagation delay < 2.5 ns (max)

Very low duty cycle distortion < 270 ps (max)

Very low CMOS power levels

Operating frequency up to 166 MHz

TTL compatible inputs and outputs

Inputs can be driven from 3.3 V or 5 V components

Two independent output banks with 3-state control

Available in SSOP and QSOP packages