ONSEMIMC14043BDGIC: digital
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input, a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs. Double Diode Input Protection Three-State Outputs with Common Enable Outputs Capable of Driving Two Low-power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range Supply Voltage Range = 3.0 Vdc to 18 Vdc Pb-Free Packages are Available
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input, a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.
Double Diode Input Protection
Three-State Outputs with Common Enable
Outputs Capable of Driving Two Low-power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Pb-Free Packages are Available