Renesas Electronics 9DB102BGILF, LVDS Buffer Dual TTL Buffer, 20-Pin TSSOP [9DB102BGILF]; 217-7928

The Renesas Electronics 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.

2 - 0.7 V HCSL differential output pairs

Phase jitter: PCIe Gen2 < 3.1 ps rms

Phase jitter: PCIe Gen1 < 86 ps peak to peak

Supports zero delay buffer mode and fanout mode

Bandwidth programming available

33-110 MHz operation in PLL mode

10-110 MHz operation in Bypass mode