STMicroelectronics IC: driver; SiC MOSFET gate driver; SO36-W; -4÷4A; 1.2kV; Ch: 2 [STGAP2SICDTR]
The STMicroelectronics STGAP2SiCD is a dual gate driver for SiC MOSFETs which provides galvanic isolation between each gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A current capability and rail-to-rail outputs, making it suitable for mid and high power applications such as power conversion and industrial motor drivers inverters. The separated output pins allow to independently optimize turn-on and turn-off by using dedicated gate resistors, while the Miller CLAMP function allows avoiding gate spikes during fast commutations in half-bridge topologies. The device integrates protection functions: dedicated SD and BRAKE pins are available, UVLO and thermal shutdown are included to easily design high reliability systems. 4 A Miller CLAMP UVLO function Configurable interlocking function Dedicated SD and BRAKE pins Gate driving voltage up to 26 V 3.3 V, 5 V TTL/CMOS inputs with hysteresis Temperature shutdown protection Standby function 6 kV galvanic isolation Wide Body SO-36W In half-bridge topologies the interlocking function prevents outputs from being high at the same time, avoiding shoot-through conditions in case of wrong logic input commands. The interlocking function can be disabled by a dedicated configuration pin, allowing independent and parallel operation of the two channels. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption.
The STMicroelectronics STGAP2SiCD is a dual gate driver for SiC MOSFETs which provides galvanic isolation between each gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A current capability and rail-to-rail outputs, making it suitable for mid and high power applications such as power conversion and industrial motor drivers inverters. The separated output pins allow to independently optimize turn-on and turn-off by using dedicated gate resistors, while the Miller CLAMP function allows avoiding gate spikes during fast commutations in half-bridge topologies. The device integrates protection functions: dedicated SD and BRAKE pins are available, UVLO and thermal shutdown are included to easily design high reliability systems.
4 A Miller CLAMP
UVLO function
Configurable interlocking function
Dedicated SD and BRAKE pins
Gate driving voltage up to 26 V
3.3 V, 5 V TTL/CMOS inputs with hysteresis
Temperature shutdown protection
Standby function
6 kV galvanic isolation
Wide Body SO-36W
In half-bridge topologies the interlocking function prevents outputs from being high at the same time, avoiding shoot-through conditions in case of wrong logic input commands. The interlocking function can be disabled by a dedicated configuration pin, allowing independent and parallel operation of the two channels. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption.