STMicroelectronics IC: STM32 ARM microcontroller; 216MHz; LQFP64; 1.7÷3.6VDC [STM32F722RET6]
STM32F7 Series Microcontrollers, STMicroelectronics The STM32F7xx microcontrollers are based on the high-performance ARM Cortex-M7 32-bit RISC core. The STM32F7 microcontrollers feature ST's ART Accelerator™ as well as an L1 cache and deliver the maximum theoretical performance of the ARM Cortex-M7 core, regardless if code is executed from embedded Flash or external memory. Typical performance figures: 1082 CoreMark / 462 DMIPS at 216MHz clock frequency. AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories Double-Precision Floating-Point maths unit on some variants Up to 16KB +16KB of I-cache and D-cache Up to 2MB of embedded Flash memory, with Read-While-Write capability on certain devices Up to 512KB of data memory, including up to 128KB of Tightly-Coupled Memory for Data (DTCM) for Stacks, Heaps 16KB of Tightly-Coupled Memory for Instructions (ITCM) for time-critical routines 4KB of backup SRAM to keep data in the lowest power modes Peripheral speed is independent from CPU speed (dual clock support) Protected code execution feature (PC-ROP) on some variants Power Efficiency: 7 CoreMark/mW at +1.8Vdc
STM32F7 Series Microcontrollers, STMicroelectronics
The STM32F7xx microcontrollers are based on the high-performance ARM Cortex-M7 32-bit RISC core.
The STM32F7 microcontrollers feature ST's ART Accelerator™ as well as an L1 cache and deliver the maximum theoretical performance of the ARM Cortex-M7 core, regardless if code is executed from embedded Flash or external memory. Typical performance figures: 1082 CoreMark / 462 DMIPS at 216MHz clock frequency.
AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories
Double-Precision Floating-Point maths unit on some variants
Up to 16KB +16KB of I-cache and D-cache
Up to 2MB of embedded Flash memory, with Read-While-Write capability on certain devices
Up to 512KB of data memory, including up to 128KB of Tightly-Coupled Memory for Data (DTCM) for Stacks, Heaps
16KB of Tightly-Coupled Memory for Instructions (ITCM) for time-critical routines
4KB of backup SRAM to keep data in the lowest power modes
Peripheral speed is independent from CPU speed (dual clock support)
Protected code execution feature (PC-ROP) on some variants
Power Efficiency: 7 CoreMark/mW at +1.8Vdc