STMicroelectronics IC: ARM microprocessor; Architecture: ARM,Cortex A35,Cortex M33; STM32MP253CA-STM-0 [STM32MP253CAL3]
The STMicroelectronics ARM Microcontroller is based on the high performance single or dual core Arm Cortex-A35 64 bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32 Kbyte L1 instruction cache for each CPU, a 32 Kbyte L1 data cache for each CPU, and a 512 Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8 stage in order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency. The Cortex-M33 core features a floating point unit single precision which supports Arm single precision data processing instructions and data types. The Cortex-M33 supports a full set of DSP instructions, TrustZone and a memory protection unit which enhances application security. Reset and power management function Low power consumption Clock management Interconnect matrix 4 DMA controllers to unload the CPU Up to 51 communication peripherals 7 analogue peripherals Video processing Up to 34 timers and 7 watchdogs Hardware acceleration Artificial intelligence and graphics supported
The STMicroelectronics ARM Microcontroller is based on the high performance single or dual core Arm Cortex-A35 64 bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32 Kbyte L1 instruction cache for each CPU, a 32 Kbyte L1 data cache for each CPU, and a 512 Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8 stage in order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency. The Cortex-M33 core features a floating point unit single precision which supports Arm single precision data processing instructions and data types. The Cortex-M33 supports a full set of DSP instructions, TrustZone and a memory protection unit which enhances application security.
Reset and power management function
Low power consumption
Clock management
Interconnect matrix
4 DMA controllers to unload the CPU
Up to 51 communication peripherals
7 analogue peripherals
Video processing
Up to 34 timers and 7 watchdogs
Hardware acceleration
Artificial intelligence and graphics supported