ALLIANCE MEMORYAS4C64M16D3B-12BINAS4C64M16D3B-12BIN, SDRAM 1GByte Through Hole, 800MHz, 78-Pin 78-ball FBGA

The Alliance Memory Synchronous DRAM is based on a double data rate architecture to achieve high-speed operation and is internally configured as eight banks. The 1Gb chip is organized as 8Mbit x 16 I/Os across 8 banks. It supports double-data-rate transfer speeds up to 1600 Mb/sec per pin for general applications. The design complies with DDR3 standards, with all control and address inputs synchronized to a pair of externally supplied differential clocks.

Fully synchronous operation

8 internal banks for concurrent operation

Pipelined internal architecture