Microchip Technology24FC512T-I/SNIC: EEPROM memory
The Microchip 512 Kbit Electrically Erasable PROM organized as a single block of 64K x 8 bit memory with a two wire serial interface. Its low voltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 400 μA, respectively. It also has a page write capability for up to 128 bytes of data. This device is capable of both random and sequential reads up to the 512K boundary. Two wire serial interface and I2C compatible Cascadable for up to eight devices Schmitt trigger inputs for noise suppression Output slope control to eliminate ground bounce 128 byte page write buffer
The Microchip 512 Kbit Electrically Erasable PROM organized as a single block of 64K x 8 bit memory with a two wire serial interface. Its low voltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 400 μA, respectively. It also has a page write capability for up to 128 bytes of data. This device is capable of both random and sequential reads up to the 512K boundary.
Two wire serial interface and I2C compatible
Cascadable for up to eight devices
Schmitt trigger inputs for noise suppression
Output slope control to eliminate ground bounce
128 byte page write buffer