Microchip TechnologyDSPIC33CH512MP508-I/PTIC: dsPIC microcontroller
The Microchip dsPIC33CH512MP508 digital signal controllers (DSCs) feature dual 90 & 100 MIPS 16-bit dsPIC® DSC cores with integrated DSP and enhanced on-chip peripherals. It operates on 3V to 3.6V voltage range. It has 512-Kbyte Program Memory, 48KB DSC enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. It can be used to control BLDC, PMSM, ACIM, SR and stepper motors. This DSC enable the design of switched mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC and other power circuits to reach the highest possible energy efficiency. Master Core 90 MIPS and Slave Core 100 MIPS Operation Independent Peripherals for Master Core and Slave Core High Speed PWMs with 250ps resolution, 12x2 Channel Configurable Shared Resources for Master Core and Slave Core Fast 6-Cycle Divide Zero Overhead Looping Multiple redundant clock sources I/O Port read-back Analog peripherals redundancies Windowed Watchdog Timer RAM BIST Hardware traps SFR locks Write protection Shadow working registers Temperature range between -40°C to +85°C Plastic Thin Quad Flatpack – (64-pin) 10x10 mm body (TQFP)
The Microchip dsPIC33CH512MP508 digital signal controllers (DSCs) feature dual 90 & 100 MIPS 16-bit dsPIC® DSC cores with integrated DSP and enhanced on-chip peripherals. It operates on 3V to 3.6V voltage range. It has 512-Kbyte Program Memory, 48KB DSC enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. It can be used to control BLDC, PMSM, ACIM, SR and stepper motors. This DSC enable the design of switched mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC and other power circuits to reach the highest possible energy efficiency.
Master Core 90 MIPS and Slave Core 100 MIPS Operation
Independent Peripherals for Master Core and Slave Core
High Speed PWMs with 250ps resolution, 12x2 Channel
Configurable Shared Resources for Master Core and Slave Core
Fast 6-Cycle Divide
Zero Overhead Looping
Multiple redundant clock sources
I/O Port read-back
Analog peripherals redundancies
Windowed Watchdog Timer
RAM BIST
Hardware traps
SFR locks
Write protection
Shadow working registers
Temperature range between -40°C to +85°C
Plastic Thin Quad Flatpack – (64-pin) 10x10 mm body (TQFP)