RENESAS ELECTRONICS9DB233AGILF9DB233AGILF Clock Buffer 20-Pin TSSOP
Maximum Input Frequency 110MHzMaximum Supply Current 80mAKiểu lắp SMDNumber of Elements per Chip 4
Liên hệ
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS